With aggressive process scaling, a raw bit error rate (RBER) of NAND flash memory is increasing. To maintain a particular level of reliability, solid-state drive/disk (SSD) controllers are adopting soft decoded error correction codes, such as low density parity check (LDPC) codes. Soft decoded error correction codes are more powerful in correcting errors, but need soft information as an input to the decoder. The soft information is typically in the form of a log likelihood ratio (LLR). Conventional flash devices do not provide soft decisions. The SSD controllers have to calculate the soft decisions using either hardware or software. In order to calculate LLRs, information about cell voltage distributions is needed. For different types of NAND flash memory, the number of programmed cell voltage distributions is different. A characteristic of NAND flash channels is that the cell voltage distributions can change with a number of factors. Factors that affect the cell voltage distributions include number of program and erase cycles (PEC), retention time, temperature, and read disturb. In order to keep the information about the cell voltage distributions up-to-date, the SSD controllers repeatedly estimate the cell voltage distributions. The repeated estimation of the cell voltage distributions is called channel tracking. The mean of the voltage distribution for an erase state of NAND flash memory can be well below zero volts for small PEC numbers. Because existing NAND flash memory does not allow reading to negative voltages in normal operation mode, tracking the erase state of the NAND flash memory is problematic. Without erase state tracking, setting read reference voltage (Vref) and calculating LLRs becomes unreliable. It would be desirable to have a method of erase state handling in flash channel tracking that solves this problem.